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1 datasheet intelligent digital amplifier and sound processor d2-7xx83 the d2-7xx83 family of the dae-6? digital audio engine? devices are complete system-o n chip (soc) audio processor and class-d amplifier controllers. integrated dsp processing and configurable audio proce ssing algorithms provide an extremely flexible platform for feature rich and cost-effective quality audio solutions which be nefit from the addition of class-d amplifiers and dsp audio processing, meeting demands of consumer electronics applications. the 12 integrated digital pwm controllers can be used in a variety of multi-channel audio system configurations, supporting powered as well as line outputs. fully protected amplifier control provides efficient and clean class-d power output support. the dae-6? device family supports full audio decoding for formats including dolby ? digital, dolby ? pro logic iix, aac lc?, dts ? digital surround, dts ? es, and dts neo:6 ? . the dae-6 is pin-compatible an d function/feature compatible with the dae-3? devices, enabling additional decoding capability to existing designs, or providing cost optimization to lower-featured systems not requiring the additional audio processing and decode capability. applications ? audio video receiver (avr) ?dtv soundbar ? home theater in a box (htib) ? multi-channel multi-media (mm) systems ? multi-room distributed audio (mrda) ? powered speaker systems ? automotive trunk/amplified solutions features ? advanced dae-6? digital audio engine? ic - pin compatible and function/feature compatible with the d2audio? dae-3? device ? total system on chip (soc) - all digital class-d amplifier controller - full 5.1/7.1/9.1-channel amplifier platform support ? enhanced audio processing decoders -dolby ? digital/ac3 -dolby ? pro logic iix -aaclc? -dts ? digital surround -dts ? es -dtsneo:6 ? ? d2audio? soundsuite? enhancement and virtualization ? mark levinson mightycat? audio enhancement ? expanded on-chip memory capacity ? integrated dsp processing - 12 channels of digital signal processing (dsp) including equalizers, filters, mixers and other common audio processing blocks - fully configurable and routable audio signal paths ? flexible audio input and output configurations ? embedded 8-channel sample rate converter - sample rates from 32khz up to 192khz ? real-time amplifier control and monitoring - supports bridged, half-bridged, and bridge-tied load (btl) topologies, using discrete or integrated power stages from 10w to over 500w - complete fault protection with automatic recovery april 28, 2016 fn7838.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2011, 2016. all rights reserved intersil (and design), dae-6 and d2audio are trademarks ow ned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
d2-7xx83 2 fn7838.3 april 28, 2016 submit document feedback ordering information part number ( note 2 ) part marking audio processing feature set support ( note 1 ) temp. range (c) package (rohs compliant) pkg. dwg. # d2-71083-lr d2-71083-lr refer to table 1 -10 to +85 128 ld lqfp q128.14x14 d2-74083-lr d2-74083-lr refer to table 1 -10 to +85 128 ld lqfp q128.14x14 d2-71583-lr d2-71583-lr refer to table 1 -10 to +85 128 ld lqfp q128.14x14 D2-74583-LR D2-74583-LR refer to table 1 -10 to +85 128 ld lqfp q128.14x14 d2-71683-lr (no longer available, recommended replacement: d2-71583-lr) d2-71683-lr refer to table 1 -10 to +85 128 ld lqfp q128.14x14 d2mc-72083-lr (no longer available or supported) d2mc-72083-lr refer to table 1 -10 to +85 128 ld lqfp q128.14x14 d2mc-76083-lr (no longer available or supported) d2mc-76083-lr refer to table 1 -10 to +85 128 ld lqfp q128.14x14 notes: 1. the d2-7xx83 devices support multiple audio processing algorithms and decoders, and support is device-dependent. refer to table 1 for the supported features for each device part number. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. .for moisture sensitivity level (msl), please see product information page for d2-71083 , d2-74083 , d2-71583 , d2-74583 , d2-71683 , d2mc-72083 , d2mc-76083 . for more information on msl, please see tech brief tb363 .
d2-7xx83 3 fn7838.3 april 28, 2016 submit document feedback dae-6 device feature set offering the d2-7xx83 family has specific part numbers to specify the feat ures and algorithms supported in the device. these part number s their supported features are shown in table 1 . table 1. dae-6 device part numbers and features part number features algorithm support dsp clock and memory ( note 4 ) d2-71083-lr 8-channels audio of i 2 s digital inputs 2 s/pdif digital inputs 8 audio processing channels with pwm outputs embedded 8-channel sample rate converter d2audio? soundsuite? audio processing 147mhz dsp clock 24k x and y memory capacities 32k p memory capacity d2-74083-lr 8-channels audio of i 2 s digital inputs 2 s/pdif digital inputs 8 audio processing channels with pwm outputs embedded 8-channel sample rate converter d2audio? soundsuite? audio processing 160mhz dsp clock 40k x and y memory capacities 56k p memory capacity d2-71583-lr 8-channels audio of i 2 s digital inputs 2 s/pdif digital inputs 8 audio processing channels with pwm outputs embedded 8-channel sample rate converter d2audio? soundsuite? dolby? digital/ac3 decoder dolby? pro logic iix surround dts? digital surround decoder 147mhz dsp clock 24k x and y memory capacities 32k p memory capacity D2-74583-LR 8-channels audio of i 2 s digital inputs 2 s/pdif digital inputs 8 audio processing channels with pwm outputs embedded 8-channel sample rate converter d2audio? soundsuite? dolby? digital/ac3 decoder dolby? pro logic iix surround dts? digital surround decoder 160mhz dsp clock 40k x and y memory capacities 56k p memory capacity d2-71683-lr (no longer available, recommended replacement: d2-71583-lr) 8-channels audio of i 2 s digital inputs 2 s/pdif digital inputs 8 audio processing channels with pwm outputs embedded 8-channel sample rate converter d2audio? soundsuite? dolby? digital/ac3 decode processing dolby? pro logic iix surround processing dts? digital surround decode processing aac lc? decode processing 147mhz dsp clock 24k x and y memory capacities 32k p memory capacity d2mc-72083-lr (no longer available or supported) 8-channels audio of i 2 s digital inputs 2 s/pdif digital inputs 8 audio processing channels with pwm outputs embedded 8-channel sample rate converter mark levinson mightycat? audio processing 147mhz dsp clock 24k x and y memory capacities 32k p memory capacity d2mc-76083-lr (no longer available or supported) 8-channels audio of i 2 s digital inputs 2 s/pdif digital inputs 8 audio processing channels with pwm outputs embedded 8-channel sample rate converter mark levinson mightycat? audio processing 160mhz dsp clock 40k x and y memory capacities 56k p memory capacity note: 4. 147mhz dsp clock speed represents an actual dsp clock of 147. 456mhz, and 160mhz dsp clock speed represents an actual dsp cloc k of 159.744mhz, when using a crystal frequency of 24.576mhz.
d2-7xx83 4 fn7838.3 april 28, 2016 submit document feedback table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 dae-6 device feature set offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial audio interface port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 two-wire (i 2 c) interface port timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 spi? interface port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 target performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 application markets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 system features and support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 audio processing signal flow su pport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 audio input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 audio output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 hd audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 sample rate converters (src) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 dsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 clocks and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 hardware i/o functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 amplifier protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 booting and boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 control interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 audio processing functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 firmware functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 input source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 master volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 channel attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 excursion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 compressor/limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 upward compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 high/low-pass filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 routers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 loudness contour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 audio processing enhancements and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 soundsuite? processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mark levinson mightycat? processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 disclaimer for dolby technology license required notice:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 disclaimer for dts (srs) technology license required notice: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 low plastic quad flatpack packages (lqfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
d2-7xx83 5 fn7838.3 april 28, 2016 submit document feedback absolute maximum ratings ( note 7 ) thermal information supply voltage rvdd, pwmvdd, adcvdd . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 4.0v cvdd, pllvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.4v input voltage any input but xtali . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to rvdd +0.3v xtali . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to pllvdd +0.3v input current, any pin but supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 128 ld lqfp package ( notes 5 , 6 ) . . . . . . 40 6.5 maximum storage temperature. . . . . . . . . . . . . . . . . . . . -55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10c to +85c digital i/o supply voltage, pwmvdd . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3v core supply voltage, cvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8v analog supply voltage, pllvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. for ? jc , the ?case temp? location is taken at the package top center. 7. absolute maximum parameters are not tested in production. electrical specifications ta = +25c, cvdd = pllvdd = 1.8v 5%, rvdd = pwmv dd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. pll at 294.912mhz, osc at 24.576mhz, core running at 147.456mhz with typical audio data traffic. minimum supply currents are measured in full power down configuration. symbol parameter test conditions min ( note 11 )typ max ( note 11 )unit v ih digital input high logic level ( note 8 ) rvdd = 3.3v (scales with rvdd) 2.0 - - v v il digital input low logic level ( note 8 ) rvdd = 3.3v (scales with rvdd) --0.8v v oh high level output drive voltage (i out at - pin drive strength current, see ? pin descriptions ? on page 11 ) rvdd - 0.4 - - v v ol low level output drive voltage (i out at + pin drive strength current, see ? pin descriptions ? on page 11 ) --0.4v vihx high level input drive voltage xtali pin 0.7 - pllvdd v vilx low level input drive voltage xtali pin - - 0.3 v i in input leakage current ( note 9 )--10a c in input capacitance -9-pf voho high level output drive voltage oscout pin pllvdd - 0.3 - - v volo low level output drive voltage oscout pin - - 0.3 v c out output capacitance - 9 - pf t rst nreset pulse width - 10 - ns r vdd / pwm vdd typical digital and pwm i/o pad ring supply (voltage) 3.0 3.3 3.6 v (current, active) - 15 - ma (current, power-down) - <1 - ma cvdd typical core supply (voltage) 1.7 1.8 1.9 v (current, active) - 450 - ma (current, power-down) - 15 - ma pllvdd typical pll analog supply ( voltage) 1.7 1.8 1.9 v (current, active) - 25 - ma (current, power-down) - 10 - ma
d2-7xx83 6 fn7838.3 april 28, 2016 submit document feedback adcvdd typical adc analog supply (voltage) 3.0 3.3 3.6 v (current, active, power-down) - 12 - ma crystal oscillator xo crystal frequency (fundamental mode crystal) 20 24.576 24.822 (24.576 + 1%) mhz dt duty cycle 40 - 60 % t start start-up time (start-up ti me is oscillator enabled (with valid supply) to stable oscillation) -520ms pll f vco vco frequency 80.00 294.912 297.86 mhz f in input reference frequency 20 - 24.822 (24.576 + 1%) mhz feedback dividers (integer) 4 12 15 pll lock time from any input change - 2 - ms 1.8v power-on reset v en reset enabled voltage level - 1.1 1.4 v t rej por pulse width rejection - 150 500 ( note 12 ) s t dis por minimum output pulse width - 5 - s 1.8v brownout detection detect level 1.4 1.5 1.6 v t bod1 pulse width rejection - 100 - ns t o1 minimum output pulse width 20 - - ns 3.3v brownout detection detect level 2.5 2.7 2.9 v t bod3 pulse width rejection - 100 - ns t o3 minimum output pulse width 20 - - ns adc performance specifications v ref adcref dc level i ref = 0 1.3 1.4 1.5 v i ref adcref load current - - 20 a r ref adcref source impedance - 14 - k v ain analog input level v ref - 0.6 - v ref + 0.6 v dynamic range -94-db thd+n - -80 - db gain mismatch -0.1-db crosstalk - -80 - db power supply rejection - -70 - db notes: 8. all input pins except xtali. 9. input leakage applies to all pins except xtalo. 10. power-down is with device in reset and clocks stopped. 11. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 12. limits established by characterization and are not production tested. electrical specifications ta = +25c, cvdd = pllvdd = 1.8v 5%, rvdd = pwmv dd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. pll at 294.912mhz, osc at 24.576mhz, core running at 147.456mhz with typical audio data traffic. minimum supply currents are measured in full power down configuration. (continued) symbol parameter test conditions min ( note 11 )typ max ( note 11 )unit
d2-7xx83 7 fn7838.3 april 28, 2016 submit document feedback serial audio interface port timing ( figure 1 ) ta = +25c, cvdd = pllvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltag es referenced to ground. symbol description min ( note 11 )typ max ( note 11 )unit tc sclk sckrx frequency - sckr0, sckr1 12.5 mhz tw sclk sckrx pulse width (high and low) - sckr0, sckr1 40 ns ts lrclk lrckrx set-up to sclk rising - lrckr0, lrckr1 20 ns th lrclk lrckrx hold from sclk ri sing - lrckr0, lrckr1 20 ns ts sdi sdinx set-up to sclk rising - sdin0, sdin1 20 ns th sdi sdinx hold from sclk rising - sdin0, sdin1 20 ns t dsdo sdoutx delay from sclk falling 20 ns figure 1. serial audio interface port timing sckrx t h lrclk lrclkrx sdinx sdoutx t c sclk t w sclk t w sclk t s sdi t h sdi t s lrclk t d sdo
d2-7xx83 8 fn7838.3 april 28, 2016 submit document feedback two-wire (i 2 c) interface port timing ( figure 2 ) ta = +25c, cvdd = pllvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. symbol description min ( note 11 ) typical max ( note 11 )unit f scl scl frequency 100 khz t buf bus free time between transmissions 4.7 s tw lowsclx scl clock low 4.7 s tw highsclx scl clock high 4.0 s ts sta set-up time for a (repeated) start 4.7 s th sta start condition hold time 4.0 s th sdax sda hold from scl falling ( note 13 ) 1 s ts sdax sda set-up time to scl rising 250 ns td sdax sda output delay time from scl falling ( note 14 )3.5s t r rise time of both sda and scl ( note 14 )1s t f fall time of both sda and scl ( note 14 ) 300 ns ts sto set-up time for a stop condition 4.7 s note: 13. data is clocked in as valid on next xtali rising edge after scl goes low. 14. limits established by characteri zation and not production tested. figure 2. i 2 c interface timing t whigh sclx t wlow sclx sclx t s sta sdax (input) sdax (output) t h sdax tssdax t buf t s sto t f t r t h stax t d sdax
d2-7xx83 9 fn7838.3 april 28, 2016 submit document feedback spi? interface port timing ( figure 3 ) ta = +25c, cvdd = pllvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. symbol description min ( note 11 ) max ( note 11 )unit spi master mode timing t v mosi valid from clock edge - 8 ns t s miso set-up to clock edge 10 - ns t h miso hold from clock edge 1 system clock + 2ns t wi nss minimum width 3 system clocks + 2ns spi slave mode timing t v miso valid from clock edge 3 system clocks + 2ns t s mosi set-up to clock edge 10 - ns t h mosi hold from clock edge 1 system clock + 2ns t wi nss minimum width 3 system clocks + 2ns figure 3. spi timing sck (cpha = 1, cpol = 0 sck (cpha = 0, cpol = 0 mosi miso (cpha = 0 t v t v t s t h t wi nss
d2-7xx83 10 fn7838.3 april 28, 2016 submit document feedback pin configuration d2-71083, d2-74083, d2-71583, d2-74583, d2-71683, d2mc-72083, d2mc-76083 (128 ld lqfp) top view sc20 srd2 sc21 sck2 std2 sc22 mclk sck3 std3 sc32 sc30 sc31 srd3 std0 sck0 cvdd cvdd cgnd cgnd rgnd rvdd srd0 sc00 sc01 sck tio1 miso mosi gpio7 gpio3 sc02 gpio2 pwmvdd pwm0 pwm1 pwm2 pwm3 pwmgnd pwmvdd pwm4 pwm5 pwm6 pwm7 pwmgnd pwmvdd pwm8 pwm9 pwm10 pwm11 pwm12 pwm13 pwmgnd pwmvdd pwm14 pwm15 pwm16 pwmgnd cvdd cgnd rgnd rvdd gpio1 pwm17 protect2 scl0 sda0 gpio0 protect0 protect1 tio0 nreset nrstout srd1 sck1 std1 sc10 sc11 sc12 cvdd cgnd rgnd rvdd nss ntrst adcgnd ain0 adcref ain1 pllavdd xtalo xtali plltesta plltestb pllagnd adcvdd oscout gpio4 gpio5 gpio6 sda1 scl1 protect9 spdifrx1 spdiftx test irqa irqb irqc irqd tio2 cvdd cvdd cgnd cgnd rgnd rvdd pumphi pssync pwmsync protect3 protect4 protect5 protect6 protect7 spdifrx0 pstemp pscurr pumplo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 25 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 71 70 69 68 67 66 72 65 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 103 102 101 100 99 98 104 97 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 58 59 60 61 62 63 57 64
d2-7xx83 11 fn7838.3 april 28, 2016 submit document feedback pin descriptions pin pin name ( note 15 )type voltage level (v) drive strength (ma) description 1 sc20 i/o 3.3 8 serial audio interface 2, i 2 s0 sclk 2 srd2 i/o 3.3 4 serial audio interface 2, i 2 s0 sdin 3 sc21 i/o 3.3 8 serial audio interface 2, i 2 s0 lrck 4 sck2 i/o 3.3 8 serial audio interface 2, i 2 s1 sclk 5 std2 i/o 3.3 8 serial audio interface 2, i 2 s1 sdin 6 sc22 i/o 3.3 4 serial audio interface 2, i 2 s1 lrck 7mclk o 3.3 16i 2 s serial audio master clock output for extern al adc/dac components, drives low on reset and is enabled by firmware assignment. 8 sck3 i/o 3.3 8 serial audio interface 3, i 2 s3 sclk 9 std3 i/o 3.3 8 serial audio interface 3, i 2 s3 sdin 10 sc32 i/o 3.3 8 serial audio interface 3, i 2 s3 lrck 11 sc30 i/o 3.3 8 serial audio interface 3, i 2 s2 sclk 12 sc31 i/o 3.3 8 serial audio interface 3, i 2 s2 lrck 13 srd3 i/o 3.3 4 serial audio interface 3, i 2 s2 sdin 14 std0 i/o 3.3 8 serial audio interface 0, i 2 s sdat0 15 sck0 i/o 3.3 8 serial audio interface 0, i 2 s lrck0 16 cvdd p 3.3 core power, 1.8v 17 cvdd p 3.3 core power, 1.8v 18 cgnd p 3.3 core ground 19 cgnd p 3.3 core ground 20 rgnd p 3.3 digital pad ring ground. internally connected to pwmgnd. 21 rvdd p 3.3 digital pad ring power, 3.3v. this 3.3v su pply is used for all the digital i/o pad drivers and receivers, except for the analog pa ds. internally connected to pwmvdd. 22 srd0 i/o 3.3 4 serial audio interface 0, sdio, defaults to input, and may be configured as gpio by firmware. 23 sc00 i/o 3.3 8 serial audio interface 0, sdio, defaults to input, and may be configured as gpio by firmware. 24 sc01 i/o 3.3 8 serial audio interface 0, i 2 s sdat1 25 sc02 i/o 3.3 8 serial audio interface 0, i 2 s lrck1 26 sck i/o 3.3 4 spi clock i/o with hysteresis input. 27 tio1 i/o 3.3 16 timer i/o port 1. operation and assignment is controlled by firmware. leave unconnected when not in use. 28 miso i/o 3.3 4 spi master input, slave output data signal. 29 mosi i/o 3.3 4 spi master output, slave input data signal. 30 gpio7 i/o 3.3 16 general purpose i/o bidirectional gpio port. (one of 8 gpio. resets to input port. operation and assignment is defined by product application's firmware.) 31 gpio3 i/o 3.3 16 general purpose i/o bidirectional gpio port. (one of 8 gpio. resets to input port. operation and assignment is defined by product application's firmware.) 32 gpio2 i/o 3.3 16 general purpose i/o bidirectional gpio port. (one of 8 gpio. resets to input port. operation and assignment is defined by product application's firmware.) 33 gpio4 i/o 3.3 16 general purpose i/o bidirectional gpio port. (one of 8 gpio. resets to input port. operation and assignment is defined by product application's firmware.)
d2-7xx83 12 fn7838.3 april 28, 2016 submit document feedback 34 gpio5 i/o 3.3 16 general purpose i/o bidirectional gpio port. (one of 8 gpio. resets to input port. operation and assignment is defined by product application's firmware.) 35 gpio6 i/o 3.3 16 general purpose i/o bidirectional gpio port. (one of 8 gpio. resets to input port. operation and assignment is defined by product application's firmware.) 36 sda1 i/o 3.3 8 - od two-wire serial data port 1. bidirectional signal used by both the master and slave controllers for data transport. 37 scl1 i/o 3.3 8 - od two-wire serial clock port 1. bidirectional signal is used by both the master and slave controllers for clock signaling. 38 protect9 i/o 3.3 4 pwm protection inpu t with hysteresis. (one of 9 protec tion inputs. specific function and channel assignment is defined by firmware.) 39 spdifrx1 i 3.3 - s/pdif digital audio data input 1 40 spdifrx0 i 3.3 - s/pdif digital audio data input 0 41 spdiftx o 3.3 4 s/pdif digital audio output. (audio cont ent and audio processing signal flow is dependent upon firmware, driving stereo output up to 192khz.) 42 test i 3.3 - factory test use only. must be tied low. 43 irqa i 3.3 - interrupt request port a, boot mode select. one of 4 irq pins. connects to logic high (3.3v) or to ground & high/low logic status establishes boot mode selection upon de-assertion of reset (nreset) cycle. 44 irqb i 3.3 - interrupt request port b, boot mode select. one of 4 irq pins. connects to logic high (3.3v) or to ground & high/low logic status establishes boot mode selection upon de-assertion of reset (nreset) cycle. 45 irqc i 3.3 - interrupt request port c, boot mode select . one of 4 irq pins. connects to logic high (3.3v) or to ground & high/low logic status establishes boot mode selection upon de-assertion of reset (nreset) cycle. 46 irqd i 3.3 - interrupt request port d, boot mode select. one of 4 irq pins. connects to logic high (3.3v) or to ground & high/low logic status establishes boot mode selection upon de-assertion of reset (nreset) cycle. 47 tio2 i/o 3.3 16 timer i/o port 2. operation and assign ment is controlled by firmware. leave unconnected when not in use. 48 cvdd p 3.3 - core power, 1.8v 49 cvdd p 3.3 - core power, 1.8v 50 cgnd p 3.3 - core ground 51 cgnd p 3.3 - core ground 52 rgnd p 3.3 - digital pad ring ground. internally connected to pwmgnd. 53 rvdd p 3.3 - digital pad ring power, 3.3v. this 3.3v su pply is used for all the digital i/o pad drivers and receivers, except for the analog pa ds. internally connected to pwmvdd. 54 pumphi i/o 3.3 16 assignable i/o. function and operation defined by firmware. 55 pumplo i/o 3.3 16 assignable i/o. function and operation defined by firmware. 56 pssync i/o 3.3 16 synchronizing output signal to swit ching power supply. (operates under specification of firmware and resets to high impedance inactive state when not used.) 57 pstemp i/o 3.3 4 assignable i/o. function and operation defined by firmware. 58 pscurr i/o 3.3 4 assignable i/o. function and operation defined by firmware. 59 pwmsync i/o 3.3 16 pwm synchronization port. (function and operation is defined by firmware.) 60 protect3 i/o 3.3 4 pwm protection inpu t with hysteresis. (one of 9 protec tion inputs. specific function and channel assignment is defined by firmware.) pin descriptions (continued) pin pin name ( note 15 )type voltage level (v) drive strength (ma) description
d2-7xx83 13 fn7838.3 april 28, 2016 submit document feedback 61 protect4 i/o 3.3 4 pwm protection inpu t with hysteresis. (one of 9 protec tion inputs. specific function and channel assignment is defined by firmware.) 62 protect5 i/o 3.3 4 pwm protection inpu t with hysteresis. (one of 9 protec tion inputs. specific function and channel assignment is defined by firmware.) 63 protect6 i/o 3.3 4 pwm protection inpu t with hysteresis. (one of 9 protec tion inputs. specific function and channel assignment is defined by firmware.) 64 protect7 i/o 3.3 4 pwm protection inpu t with hysteresis. (one of 9 protec tion inputs. specific function and channel assignment is defined by firmware.) 65 protect2 i/o 3.3 4 pwm protection inpu t with hysteresis. (one of 9 protec tion inputs. specific function and channel assignment is defined by firmware.) 66 gpio1 i/o 3.3 16 general purpose i/o bidirectional gpio port. (one of 8 gpio. resets to input port. operation and assignment is defined by product application's firmware.) 67 rvdd p 3.3 - digital pad ring power, 3.3v. this 3.3v su pply is used for all the digital i/o pad drivers and receivers, except for the analog pa ds. internally connected to pwmvdd. 68 rgnd p 3.3 - digital pad ring ground. internally connected to pwmgnd. 69 cgnd p 3.3 - core ground 70 cvdd p 3.3 - core power, 1.8v 71 pwmgnd p 3.3 - pwm output pin ground. internally connected to rgnd. 72 pwm17 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 73 pwm16 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 74 pwm15 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 75 pwm14 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 76 pwmvdd p 3.3 - pwm output pin power. this 3.3v supply is used for the pwm pad drivers. internally connected to rvdd. 77 pwmgnd p 3.3 - pwm output pin ground. internally connected to rgnd. 78 pwm13 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 79 pwm12 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 80 pwm11 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 81 pwm10 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 82 pwm9 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 83 pwm8 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 84 pwmvdd p 3.3 - pwm output pin power. this 3.3v supply is used for the pwm pad drivers. internally connected to rvdd. 85 pwmgnd p 3.3 - pwm output pin ground. internally connected to rgnd. 86 pwm7 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) pin descriptions (continued) pin pin name ( note 15 )type voltage level (v) drive strength (ma) description
d2-7xx83 14 fn7838.3 april 28, 2016 submit document feedback 87 pwm6 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 88 pwm5 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 89 pwm4 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 90 pwmvdd p 3.3 - pwm output pin power. this 3.3v supply is used for the pwm pad drivers. internally connected to rvdd. 91 pwmgnd p 3.3 - pwm output pin ground. internally connected to rgnd. 92 pwm3 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 93 pwm2 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 94 pwm1 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 95 pwm0 i/o 3.3 8 or 16 pwm output pin. (one of 18 pwm ou tput pins. channel and operation assignment is defined by firmware.) 96 pwmvdd p 3.3 - pwm output pin power. this 3.3v supply is used for the pwm pad drivers. internally connected to rvdd. 97 oscout p 1.8 - analog oscillator output to slave d2-71x 83 devices. oscout drives a buffered version of the crystal oscillator signal from the xtali pin. 98 pllagnd p 1.8 - pll analog ground 99 plltestb o 1.8 - factory test use only. must be tied low. 100 plltesta o 1.8 - factory test use only. must be tied low. 101 xtali p 1.8 - crystal oscillator analog input port. an external clock source would be driven into the this port. in multi-d2-71x83 systems, the oscout from the master d2-71x83 would drive the xtali pin. 102 xtalo p 1.8 - crystal oscillator analog output port. when using an external clock source, this pin must be open. xtalo does not have a drive strength specification. 103 pllavdd p 1.8 - pll analog power, 1.8v 104 adcvdd p 3.3 - analog power for internal adc, 3.3v 105 ain1 i 3.3 - analog input 1 to internal adc 106 adcref o 3.3 - analog voltage reference output. must be de-coupled to analog ground with 1f capacitor. 107 ain0 i 3.3 - analog input 0 to internal adc 108 adcgnd p 3.3 analog ground for internal adc 109 ntrst i 3.3 - factory test only. must be tied high at all times. 110 nss i/o 3.3 4 spi slave select i/o. 111 rvdd p 3.3 - digital pad ring power, 3.3v. this 3.3v su pply is used for all the digital i/o pad drivers and receivers, except for the analog pa ds. internally connected to pwmvdd. 112 rgnd p 3.3 - digital pad ring ground. internally connected to pwmgnd. 113 cgnd p 3.3 - core ground 114 cvdd p 3.3 - core power, 1.8v 115 sc12 i/o 3.3 8 serial audio interface 1, lrck 116 sc11 i/o 3.3 8 serial audio interface 1, sdat3 pin descriptions (continued) pin pin name ( note 15 )type voltage level (v) drive strength (ma) description
d2-7xx83 15 fn7838.3 april 28, 2016 submit document feedback 117 sc10 i/o 3.3 8 serial audio interface 1, data (assignment by firmware control.) 118 std1 i/o 3.3 8 serial audio interface 1, sdat2 119 sck1 i/o 3.3 8 serial audio interface 1, sck 120 srd1 i/o 3.3 4 serial audio interface 1, data (assignment by firmware control.) 121 nrstout o 3.3 16 - od active low open dr ain reset output. pin drives low from por generator, 3.3v brown out detector going active, or from 1.8v brown out detector going active. this output should be used to initiate a system reset to the nreset pin upon brownout event detection. 122 nreset i 3.3 - active low reset input with hysteresis. acti vates system level reset when pulled low, initializing all internal logic and program operations. system latches boot mode selection of the irq input pins on the rising edge. 123 tio0 i/o 3.3 16 timer i/o port 0. operation and assignment is controlled by firmware. leave unconnected when not in use. 124 protect1 i/o 3.3 4 pwm protection inpu t with hysteresis. (one of 9 protec tion inputs. specific function and channel assignment is defined by firmware.) 125 protect0 i/o 3.3 4 pwm protection inpu t with hysteresis. (one of 9 protec tion inputs. specific function and channel assignment is defined by firmware.) 126 gpio0 i/o 3.3 16 general purpose i/o bidirectional gpio po rt. (one of 8 gpio. resets to input port. operation and assignment is defined by product application's firmware.) 127 sda0 i/o 3.3 8 - od two-wire serial data port 0. bidirectional signal used by both the master and slave controllers for data transport. 128 scl0 i/o 3.3 8 - od two-wire serial clock port 0. bidirectional signal is used by both the master and slave controllers for clock signaling. notes: 15. unless otherwise specified all pin names are active high. those that are active low have an ?n? prefix. 16. all power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., cvdd pins to be tied together, cgnd pins to be tied together, rvdd pins to be tied together, and rgnd pins to be tied together.) cgnd and rgnd are to be tied together o n board. rgnd and pwmgnd pins are also in ternally connected and are to be tied together. pin descriptions (continued) pin pin name ( note 15 )type voltage level (v) drive strength (ma) description
d2-7xx83 16 fn7838.3 april 28, 2016 submit document feedback functional block diagram power supply test rgnd rvdd cgnd cvdd pwmgnd pwmvdd oscvdd adcgnd adcvdd adcref pllagnd pllavd 24-bit fixed-point digital signal processor with 56-bit mac (typical signal processing blocks contained within firmware download) prot9 prot7 prot6 prot5 prot4 prot3 prot2 prot1 prot0 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 pwm9 pwm10 pwm11 pwm12 pwm13 pwm14 pwm15 pwm16 pwm17 12 channel pulse width modulator engine (via 18 pins of output) linear interpolator pwm correction noise shaper quantizer output drive 4 4 6 6 4 4 ntrst test ic and audio system control interface nreset nrstout pumphi pumplo pssync pstemp pscurr pwmsync irq[d:a] gpio[7:0] 4 8 s/pdif rx spdifrx0 spdifrx1 2:1 mux stereo adc ain0 ain1 s/pdif rx 2:1 mux spdiftx 4 serial audio interface ports (4 multifunction data type receivers/transceivers) sc32 sc31 sc30 std3 sck3 srd3 sc22 sc21 sc20 std2 sck2 srd2 sc12 sc11 sc10 std1 sck1 srd1 sc02 sc01 sc00 std0 sck0 srd0 mclk amplifier protection spi port mosi miso sck nss timer tio0 tio1 tio2 pll oscout xtali xtalo sai0 port (i2s/tdm) sai1 port (i2s/tdm) sai2 port (i2s/dsd/hda/tdm) sai3 port (i2s/tdm/dsd/adc) dsd decimator engine sample rate converters hd audio interface audio processing & virtualization algorithms firmware-dependent (d2audio soundsuite?, 3 rd -party enhancements, etc.) input selection auto detection compressed audio decoders mixers / routers a/v sync post-processing (tone control, d2audio digitaleq for speaker compensation & content eq, compressor/limite r, individual channel delays) sda1 scl1 sda0 scl0 dual port 2-wire (i 2 c-compatible) figure 4. d2-7xx83 ic functional block diagram
d2-7xx83 17 fn7838.3 april 28, 2016 submit document feedback introduction the dae-6 family of ics provide the core functionality, amplifier control, and complete audio signal processing for d2audio?s class-d amplifier solutions. a va riety of reference designs from intersil d2audio corporation include specific signal flows designed for their applications, supporting today?s design features. support is also provid ed for future planned features, with little or no ad ditional hardware or logic to enable new features. the signal flow, digital audio i/o, and amplifier hardware control support is handled completely by the dae-6 firmware. the products are targeted at high-volume home theater in a box (htib), multimedia, soundbar, and similar solutions, where rich features and cost-effective qualit y audio are required to meeting demands of current consumer electronics markets. the dae-6 devices are completely pin-compatible with the dae-3 devices, allowing full flexibility for function vs cost trade-off, providing cost-effective solutions for applications of varying end-user features and capabilities. target performance typical systems built around the dae-6 support performances that includes or exceeds: ? >110 db snr/dynamic range system support ? <0.06% thd+n at full scale at 1khz ? 20hz to 20khz audio frequency response ? scalable amplifier power control capability ? discrete component and integrated power stages using full-bridge, half-bridge, and btl output topologies ? encrypted code loads and unique decryption for each ic part number ? support for all standard audio data delivery formats and protocols employed in the target markets ?the delivery formats include: i 2 s, left-justified, time-division multiplexed (tdm), s/pdif, dsd, hda, 2-channel analog application markets the powerful dsp coupled with flexible peripherals and excellent signal processing hard ware results in a chip for solutions that cover many markets. all are characterized by the need for complex signal processing and hi gh audio channel count. typical applications include a wide va riety of cost sensitive but feature-demanding performance such as in: ? multimedia speaker solutions ? multi-driver (bi-amp, tri-amp) speaker arrays ? home theater systems with compressed audio decoder ? soundbar system solutions ? set-top box solutions ? low-cost virtualized stereo, 5.1, 7.1, and 9.1 avr systems ? mrda distributed and networked audio systems with multiple powered channels ? aftermarket/oem automotive amplifiers system features and support the dae-6 enables multiple solu tions consisting of a class-d amplifier system built around internal audio processing functional blocks. features include: ? flexible audio input and output configurations - 4 independent asynchronous i 2 s digital inputs - support of 8 audio channels of hdmi -hd audio (hda) - direct stream digital? (dsd) input support - integrated high-performance stereo adc - dual multiplexed s/pdif? digital audio inputs (linear iec-61958 pcm or compressed iec-61937 audio) - s/pdif digital audio pcm output - line-level outputs (left, right, subwoofer) using passive or active output filter stages ? flexible dsp clock speed and dsp memory capacity options - 147.456mhz dsp clock speed devices, with 24k x and y memory and 32k p memory capacity - 159.744mhz dsp clock speed devices, with 24k x and y memory and 32k p memory capacity ? real-time amplifier control and monitoring - supports bridged, half-bridged, and bridge-tied load (btl) topologies, using discrete or integrated power stages from 10w to over 500w - graceful protection and recovery - complete fault protection with automatic recovery ? serial control interface via i 2 c, hda, spi, or sci ? decoding of compressed au dio formats, including -dolby ? digital/ac3 -dolby ? pro logic iix -aac?lc -dts ? digital surround -dts ? es -dtsneo:6 ? ? audio enhancement feature support - d2audio? soundsuite? audio processing enhancement - mark levinson mightycat? audio processing enhancement
d2-7xx83 18 fn7838.3 april 28, 2016 submit document feedback audio processing signal flow support the d2-7xx83-series of ics supports a wide variety of signal flows and audio processing options th at are fully programmable and are completely defined by the system firmware and system architecture. the firmware provided for the d2-7xx83 devices is application-specific and includes its own specific signal flow and associated performance level. much of the signal flow is also hardware dependent and that hardware integrates with the full system architecture that is defined within that system?s programmed firmware. each firmware design includes a specific set of control tool support, including the d2audio? audio canvas? software and system design data. additional design-specific reference documentation is included within each firmware application design, that includes platform-specific signal flows, co ntrol registers, and descriptions of advanced processing features. the various system support capabilities include: ? flexible system configuration with 8 audio input and audio processing channels, with up to 12 audio output pwm channels, supporting differenti al or single-end pwm outputs with up to 18 pwm output pins. ? audio processing for up to 4 simultaneous stereo asynchronous digital audio inputs from a variety of sources (hda, i 2 s, hdmi, dsd, s/pdif digital) ? multiple d2-7xx83 devices may be cascaded to support higher channel count designs. functional description the d2-7xx83 family of ics, integrated into d2audio?s offerings of reference design platforms support present and future design features with little or no additi onal hardware or logic to enable new features. audio input multiple versions of the d2-7xx83 family ic-based reference designs support a wide range of ma rket applications and each of these market applications has a variety of potential audio sources such as: ? mono and stereo analog inputs ?serial audio, i 2 s and time division multiplexed (tdm) single line ?network? mode ? hd-audio interface (uaa-class driver capable) ? stereo and multichannel dsd ? s/pdif digital (iec60958-compliant and iec61937- compliant) serial audio input since most systems incorporate some mix of digital and analog inputs, the dae-6 offers a very flexible digital audio peripheral interface. the dae-6 features four independent serial audio interface (sai) ports. all sai ports support both master or slave clocking and can support sample rates from 32khz to 192khz. each sai port supports the digital audio industry i 2 s standard, which supports carrying up to 24-bit li near pcm audio words per subframe iec60958, or compressed digital audio (dolby ? digital, aac, dts ? , mpeg, etc.) packing per the iec61937 specification. the sai port also supports left-justified form atted linear pcm or compressed digital audio. each sai port supports time division multiplexing (tdm) capability (a.k.a. ?network mode?) with up to 32 words per frame. sai ports 2 and 3 (the 3rd and 4th ports) have multiplexed inputs to provide a standard input signal flow for the adc, dsd, and hda audio interfaces. all serial audio input data streams go through an sai interface, which simplifies the data flow configuration. sai data formats are shown in figure 5 . for i 2 s format, the left channel data is read when lrck is low. for the left-justified format, the left channel data is read when lrck is high. either format requires data to be valid on the rising edge of sclk and sent msb-first on sdin with 32 bits of data per channel. each set of digital inputs runs asynchronously to the others and may accept different samp le rates and formats. lrclkx sclkx serial data msb -1 -2 -3 +3 +2 +1 lsb msb -1 -2 -3 +3 +2 +1 lsb msb left channel right channel i 2 s format lrclkx left channel right channel sclkx serial data msb -1 -2 -3 +3 +2 +1 lsb msb -1 -2 -3 +3 +2 +1 lsb msb -4 left-justified -4 -1 figure 5. sai port supported data formats for de livery of linear pcm or compressed audio data
d2-7xx83 19 fn7838.3 april 28, 2016 submit document feedback s/pdif receiver the d2-7xx83 contains two input pins internally multiplexed into one iec60958 compliant s/pdif digital receiver. the receiver input pins are 3.3v cmos input level compatible, requiring external circuitry to condition the serial input. the receiver contains an input transition detector, digital pll clock recovery, and a decoder to separate audio, channel status, and user data. only the first 24-channel status bits are supported. the receiver constantly monitors the incoming data stream to detect the iec61937-1 packet headers, and if found, captures the pc and pd data words into registers. the receiver meets the jitter tolerance specified in iec60958-4. s/pdif is a commonly used interface for receiving compressed (iec61937-compliant) and stereo pcm (iec60958-compliant) audio data. this interface also supports receipt of compressed audio data that is not compliant with the iec61937 specification, but instead meets the iec60958 specification. adc input the d2-7xx83 contains a high-performance analog-to-digital converter (adc) that connects to input analog sources with a minimum of interface circuitry. at a bandwidth of 20khz at nominal voltage and temperature, the adc input of the dae-6 provides a typical thd+n (unweighted) value of -81db and an snr/dynamic range of 94db. the adc master clock can be supplied from either the low jitter pll of the d2-7xx83, or from the hd audio interface. when the pll provides the adc master clock, the adc operates synchronous to the dsp proce ssing, which minimizes noise pickup. when operated from the hd audio clock system, the adc decimator output is synchronous to the hda frame rate, eliminating the need for sample rate conversion to the hda frame rate. figure 6 shows the adc decimator frequency response over full bandwidth and passband, and figure 7 shows the adc performance with full scale input processed through the src to a 48khz sample rate. 0 0.5 1.0 1.5 2.0 2.5 3.0 x10 6 150 100 50 0 level (db) 24 bits spec frequency (hz) figure 6. adc decimator frequency re sponse (256 taps decimate by 32) 0 0.5 1.0 1.5 2.0 2.5 3.0 x10 4 -0.020 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 0.020 frequency (hz) level (db) 24 bits spec -140 -120 -100 -80 -60 -40 -20 0 0 5k 10k 15k 20k magnitude (db) frequency (hz) fs = 6.144mhz ch0 input = 1khz at 1v p-p thd + n = -81db snr = 94db figure 7. adc performance at full scale input
d2-7xx83 20 fn7838.3 april 28, 2016 submit document feedback dsd the hdmi specification (version 1.2 and later) used in tv systems supports streaming dsd encoded audio over hdmi. to support this, the system can receive an d process up to 6 dsd audio streams. the dsd interface supports both standard and phase-modulated data formats. a high-quality 16x decimator engine converts all of the dsd data streams into 24-bit pcm words with an fs of 176.4khz using a 128-tap fir filter. the dsd decimation filter has a cutoff frequency of 50khz and is optimized for passband flatness. sai ports 2 and 3 support dsd format inputs. when the dsd interface is enabled, all the pins of sai 2 and the sc21 pin of sai3 become the dsd input signals. the 6 channels of dsd audio are merged into 3 i 2 s pcm streams at a 176.4khz sample rate. these i 2 s streams are routed into both receivers on sai 2 and the first receiver of sai 3. the data is then passed to the sample rate converter (src). the src will rate-lock to the dsd input clock and attenuate any jitter in the dsd input stream. the dsd input processing clusters the dsd data into channel pairs. this allows a flexible channel count of 2, 4, or all 6 dsd data streams to be handled. using 4-channel dsd frees the sai 3 port for other uses. similarly, using only 2-channel dsd frees the second sai 2 port and the sai 3 port for other uses. the d2-7xx83 family of ics also offers digital audio format conversion support for dsd stereo format input to s/pdif or i 2 s format output, as well as dsd multichannel format input to multiple i 2 s format output. this high-quality digital audio format conversion path also offers the ability to reduce clock jitter in the audio system introduced by cert ain transmission paths such as hdmi. this technique also enables co nsumer products to output a downsampled and/or downmixed (if necessary) digital audio output for audio that may not othe rwise be made available to the consumer in the original higher-b andwidth format due to certain consumer electronic/content protection licensing restrictions. the graphs in figure 8 show the dsd decimation filter frequency response at 2 different frequency zoom levels. 0 2 4 6 8 10 12 14 x10 5 -150 -100 -50 0 frequency (hz) level (db) 24 bits spec 0 0.5 1.0 1.5 2.0 2.5 3.0 x 10 4 -0.020 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 0.020 frequency (hz) level (db) 24 bits spec figure 8. dsd decimator frequency response (128 taps decimate by 16)
d2-7xx83 21 fn7838.3 april 28, 2016 submit document feedback audio output pwm audio amplifier output the d2-7xx83 family supports multiple pwm output topologies, which enables system designs to use an output stage, which meets the cost and performance requirements of the particular application. twelve pwm channels are mapped to 18 pwm output pins by the programmed firmware. the pwm output pins are 3.3v cmos levels with either 8ma or 16ma drive capability. output topologies supported include: ? half-bridge, n+n or n+p ? full-bridge, n+n or n+p using 2-level modulation, 2 or 4-quadrant control line level output in addition to amplified outputs, the d2-7xx83 family ic also supports line-level outputs that generate a nominal 1v rms output using a simple passive filter. headphone outputs or line-level outputs that require a 2v rms (or higher output level) are also supported, using an active filter to accomplish the signal level needs. s/pdif transmitter the d2-7xx83 contains one iec60958 compatible s/pdif digital transmitter. the transmitter complies with the consumer applications defined in iec609 58-3. the transmitter supports 24-bit audio data, 24-bit user data, and 30-bit channel status data. a bit-exact pass-through mode from the selected spdifrx[1:0] input is also supported. this simplifies system designs that require that the iec61937-compliant original compressed audio bitstream be made available at the back panel of the product, as well as giving the user the capability to select a decoded (and downmixed, if necessary) iec60958-compliant stereo or mono linear pcm output for digital audio recording/playback capabilities. the d2-7xx83 family optional fi rmware offers digital audio format conversion support for i 2 s digital format input to s/pdif digital format output, as well as s/pdif digital format input to i 2 s digital format output, for all digital audio linear pcm (non-compressed) audio sources. this functionality is not available for compressed audio inputs, unless the compressed audio data is first decoded by the internal dsp, and if necessary, downmixed to 2 channels. this format conversion path offers the ability to reduce the clock jitter on the output due to the fact that both inputs (when in this mode) pass through the professional -grade sample-rate converters (src). this approach also enable s consumer products to output a downsampled digital audio output for audio that may not otherwise be made available to the consumer in the original higher-bandwidth format due to certain consumer electronic/content protection licensing restrictions. serial audio output d2-7xx83 family ic-based systems support outputting a bit-exact pass-through of a compressed audio bitstream, or a decoded, down-mixed (lt/rt or lo/ro) an d downsampled 2 channel linear pcm audio bitstream via a specified sai port, or s/pdif digital transmitter. in addition, dependin g on the firmware functionality, it is possible for unused sai (serial audio interfaces) to also support i 2 s output as well, in either slave or master mode. the output audio sample rate is determined by the firmware and can vary from 32khz up to 192khz. hd audio hda interface the hd audio interface also prov ides a control interface. this control interface uses the hd audio gpi, gpo, and gpio 8-bit ports to provide a message pa ssing facility between the d2-7xx83 and the pc. the d2-7xx83 fully supports wind ows? hardware quality labs (whql?)-certification as, it is a uaa-compliant secondary hd audio codec. the devices may be used either as the primary hda codec, or as the second hda codec in the system. features supported are: ? message passing to other devices located on the motherboard (e.g. hp jack detection and reporting.) ? amplifier firmware download. ? amplifier code load during system boot. ? amplifier control protocol (d2audio canvas ii support). hd audio play the d2-7xx83 provides for direct connection of a pc?s hd audio (hda) controller to the device. in this configuration, the d2-7xx83 functions as an hda codec with powered (amplified) outputs. supported features include: ? 2, 4, 6, or 8 amplified or pwm dac channels ? audio sample rates 48khz, 96khz, 192khz ? data widths of 16-bit, 20-bit, and 24-bit ? independent channel gain control the hda interface uses 5 of the 6 pins of the sai 3 port. the hda interface captures the audio streams and converts them into one to four i 2 s data streams, depending on the number of channels used. these i 2 s stereo streams are routed through sai 3 and sai 4 and then on to the sample rate converter. the src will rate lock to the hda stream and remove any jitter while converting the data to the output sample rate.
d2-7xx83 22 fn7838.3 april 28, 2016 submit document feedback hd audio functions and function types hd audio verbs supported table 2. function function type node id connections audio function group function group 01 parent of all other nodes, also holds gpio functions front l/r dac stereo dac 02 to front l/r mixer center/lfe dac stereo dac 03 to center/lfe mixer surround l/r dac stereo dac 04 to surround l/r mixer side surround l/r dac stereo dac 05 to side surround mixer front l/r mixer sum/mixer node 06 to front l/r pin center/lfe mixer sum/mixer node 07 to center/lfe pin surround l/r mixer sum/mixer node 08 to surround l/r pin side surround l/r mixer sum/mixer node 09 to side surround l/r pin front l/r output pin pin complex 0a to sy stem per configuration default register center/lfe output pin pin complex 0b to sy stem per configuration default register surround l/r output pin pin complex 0c to sy stem per configuration default register side surround l/r output pin pin complex 0d t o system per configuration default register table 3. verb function get code set code widget nid 01 02 - 05 06 - 09 0a - 0d converter format a 2 y gain/mute b 3 y processing coefficient c 4 coefficient index d 5 get parameter f00 yyyy connection select f01 701 get connection list f02 y y processing f03 sdi select f04 704 power state f05 705 y channel/stream id f06 706 y pin widget f07 707 y unsolicited response f08 708 pin sense f09 709 y beep f0a 70a eapd/btl f0c 70c digital converter f0d 70d - 70e volume knob f0f 70f gpi f10 - f1a 710 - 71a y config default f1c 71c - 71f y subsystem id f20 720 - 723 y
d2-7xx83 23 fn7838.3 april 28, 2016 submit document feedback hd audio widget required parameters stripe f24 724 reset 7ff y table 3. (continued) verb function get code set code widget nid 01 02 - 05 06 - 09 0a - 0d table 4. verb id - 0xf00; parameters 0x9 - 0xd node id function widget cap. pcm size rate fo rmat pin cap. input amp cap. pid 0x9 pid 0xa pid 0xb pid 0xc pid 0xd 01 function y y 02 dac y y y 03 dac y y y 04 dac y y y 05 dac y y y 06 mixer y y 07 mixer y y 08 mixer y y 09 mixer y y 0a pin y y 0b pin y y 0c pin y y 0d pin y y table 5. verb id - 0xf00; parameters 0xe - 0x13 node id function connect list length power states process cap. output amp cap. volume knob pid 0xe pid 0xf pid 0x10 pid 0x12 pid 0x13 01 function y 02 dac 03 dac 04 dac 05 dac 06 mixer y y 07 mixer y y 08 mixer y y 09 mixer y y 0a pin y y 0b pin y y 0c pin y y 0d pin y y
d2-7xx83 24 fn7838.3 april 28, 2016 submit document feedback hd audio system topology sample rate converters (src) d2-7xx83 family ics support internal asynchronous sample rate conversion to align input audio streams to a single rate compatible with the dsp processi ng rate and pwm switch rate. d2-7xx83 device family has 4 independent rate estimators, allowing up to 4 asynchronous stereo inputs (8 channels) to be sample rate converted and processed simultaneously. the sample rate converter has a measured snr that exceeds 140db and a thd+n that exceeds -125db. dsp the majority of the d2-7xx83 audio processing functions as well as system control occur within the dsp core. the core is a 24-bit fixed-point digital signal processor, tightly integrated with its own dma, interrupt control, memory, and control interfaces. software configurable processing blocks and signal routings are implemented within the dsp, allowing a wide range of functionality and system implementations through the programmed definitions that are read into memory upon device initialization. signal flows through the device are buffered and processed through hardware specific-function blocks (such as the sample rate converter) and allow considerable overall signal processing capability through interface to the dsp. clocks and pll the clock generation contains a low jitter pll critical for low noise pwm output and a precise master clock source for the adc, sample rate conversion, and the audio data paths. the serial audio interfaces can function as either a master or a slave. the pll block contains the following components: ? low noise crystal oscillator ? low jitter pll clock multiplier ?power on reset generator ? brown out detectors on the cvdd and rvdd supplies ? system reset generation logic ? clock generators for the dsp, s/pdif transmitter, adc, and mclk output pin the pll block is completely managed by the system firmware. the system clock is provided by the crystal oscillator block, using either a fundamental mode crysta l or a clock input to the xtali pin. if the clock input is used, it must be a 1.8v signal level. the input signal on the xtali pin is analog buffered and driven onto the oscout pin for use in driving the xtali input of other d2-7xx83 controllers. the pll uses the signal on the xtali pin as the reference clock. the reference clock frequency is multiplied by an integer multiple of 4 to 15 to get the pll output clock. the pll output is used to time the pwm outputs an d to generate the dsp clock. during system start-up, before the pll has been configured and locked, the pll is bypassed and the system operates at xtali speed. hda link interface front l/r dac front l/r mixer (gain control) front l/r pin complex (mute control) nid 02 nid 06 nid 0a surround l/r dac surround l/r mixer (gain control) surround l/r pin complex (mute control) nid 04 nid 08 nid 0c center / lfe dac center / lfe mixer (gain control) center / lfe pin complex (mute control) nid 03 nid 07 nid 0b side surr l/r dac side surr l/r mixer (gain control) side surr l/r pin complex (mute control) nid 05 nid 09 nid 0d figure 9. hd audio system topology
d2-7xx83 25 fn7838.3 april 28, 2016 submit document feedback the power on reset circuit senses the rise of the pllvdd supply. when the supply reaches the sense threshold, the power on reset pulse is generated. if the pllv dd supply droops below the sense threshold, the reset pulse will occur when the supply rises above the threshold. the power on rese t signal will drive the nrstout output pin low. the two power supply brown out detectors monitor the cvdd and pwmvdd power rails. if the power rail droops below the threshold, the brown out detector will activate and drive the nrstout output pin low. the system reset generation logic is activated by a low level on the nreset input pin or by the po wer on reset sensor pulse. upon de-assertion of nreset a sequenti al counter ensures sufficient time and clock cycle count for the internal synchronous logic to reset. multiple d2-7xx83 ics are capable of running on a common timebase. multiple d2-7xx83 ics synchronize themselves onto a single crystal oscillator so th at all ics run at identical frequencies. dsp clock speed and memory capacity support the d2-7xx83 devices are offered in part number-specific devices that support multiple dsp clock speeds and memory capacity. depending on the device part number, the d2-7xx83 operates up to clock rates of 147.456mhz or 159.744mhz, and offers memory capacity of 24k/24k/32k or 40k/40k, 56k of x/y/p memory space. the higher speed and larger me mory devices support designs requiring higher processing capacity, while the lower speed devices provide cost optimization to systems not requiring the additional audio processing and decode capability. refer to ? dae-6 device feature set offering ? on page 3 for the device part numbers and definitions of clock speed and memory capacity. hardware i/o functions the d2-7xx83 provides programmable i/o pins used for various hardware functions of the syst em design. pin functions are defined by the product firmware, and may be different from one design to another. general-purpose (gpio) i/o pins, eight dedicated general purpose i/o (gpio) pins are available for system use. these are controlled only by the d2-7xx83 device family firmware. timers a timer block consisting of 3 se parate general purpose timers provides programmed control of event or count down timing functions. the timer functions are controlled through the firmware, where these timers can operate as timed pulse generators, as pulse-width modulators, or as event counters to capture an event or to measure the width or period of a connected signal. these timers are connected to the 3 timer pins (tio[0:2]), which are also assi gnable as i/o by firmware. power supply synchronization the pssync pin provides a power supply synchronization signal for switching power supplies. firmware configures pssync to the frequency and duty cycle needed by the system switching regulator. the proper configuratio n eliminates audio output tones generated if the switching power supply is not locked to the amplifier switching. power supply anti-pump d2-7xx83 supports designs to co rrect for power supply pumping that occurs in half-bridge outp ut stage topologies. the pumphi and pumplo pins provide a differ ential pwm signal pair that drive an anti-pump co rrection stage. the dead time and duty cycle are adjustable to eliminat e the power supply dc offset. amplifier protection the d2-7xx83 supports individual pwm channel protection through individual protection input pins. these protect pins are primarily intended for protecting the pwm powered output stages. the protection inputs are activated by either a pulse or level driven into the pin. firmware configures the input processing logic to properly inte rpret the input signal as rising edge triggered, falling edge triggered, high level, or low level. the protection input signal is generated by specialized sensing circuits. there are several kinds of sensing circuits for detecting current, temperature, or voltage. a powered pwm output stage or a power supply pump driver typically uses an overcurrent sensor. this sensor will detect power fe t current, load current, or both. these circuits are unique to the specific power stage design, and may be embedded inside an integrated power stage. temperature and voltage sensing are accomplished in a variety of ways and usually create a dc level representing a fault condition. d2-7xx83 designs incorporate a variet y of protection strategies to prevent damage from the high voltages, currents, and temperatures present in cla ss-d amplifier designs. this protection is also effective against user-induced faults, such as clipping, output overload, or outp ut shorts, including both shorted outputs or short-to-ground faults. the d2-92xx ic works in conjunct ion with specific surrounding parts to provide continuous syst em monitoring for destructive events. these events include: ?output overcurrent ? output short circuit ? over-temperature (thermal event) ? power supply brown out ? shoot through overcurrent protection features and their de tails are firmware application dependent. firmware functions running on th e d2-7xx83 can be assigned to observe the temperature at critic al points in the hardware and automatically respond to excessi ve temperature. depending on the specific implementation, this response can be as simple as turning on an optional fan to re duce temperature, or managing the audio signal to reduce power consumption.
d2-7xx83 26 fn7838.3 april 28, 2016 submit document feedback graceful overcurrent and short circuit overcurrent sensing requires a current sensor in the power device to be protected, usually a powered pwm output. the typical sensor creates a pulse that is active when the current exceeds a specified threshold. the d2-7xx83 ic observes the overcurrent protection inputs and provides graceful protection for the output stage. the hardware is configured to provide immediate current reduction, cycle-by-cycle output clipping, output signal control, and output stage deactivation depending on the se verity and duration of high current events. the combination of hardware features and firmware monitoring allows the system to differentiate between an overcurrent situation or a more serious short circuit condition. thermal protection the d2-7xx83 ic can connect to an optional low-cost thermal sensing circuit and monitor temperatures in the system. firmware monitoring can record the system temperature and provide system responses including enabling a fan and managing the audio output signal. device operation reset and initialization the d2-7xx83 must be reset after power up to begin proper operation, and in normal system hardware configurations, the reset occurs automatically via the reset hardware circuitry. the chip contains power rail sensors, brown out detectors, on the 3.3v and 1.8v power supplies. these brown out sensors will assert and hold an internal power-on reset, which will disable the device until the power supplies are at a safe le vel for the dsp to start. these same brownout sensors will detect a power supply voltage droop while the system is active and pr ovide a safe amplifier shutdown. power sequencing the cvdd and rvdd (including pwmvdd) supplies should be brought up together to avoid high current transients that could fold back a power supply regulator. the adcvdd and pllvdd may be brought up separately. best practice would be for all supplies to feed from regulators with a common power source. typically this can be achieved by using a single 5v power source and regulating the 3.3v and 1.8v supplies from that 5v source. reset d2-7xx83 has one reset input: the nreset pin. the nreset input pin (active low, non-reset high) is effectively a power-on system reset. all internal state logic, ex cept internal test hardware, is initialized by nreset. while reset is active the system is held in the reset condition. the reset cond ition is defined as all internal reset signals being active, the crystal oscillator is running, and the pll disabled. at the de-assertion of nreset, the chip will capture the boot mode selection and begin the boot process. booting and boot modes code initialization and boot modes d2-7xx83 includes a fully-programm able dsp with internal boot rom. the boot rom?s primary function is to download a second-stage boot image from on e of several possible peripheral sources: ?i 2 c interface eeprom ?i 2 c interface slave ?spi rom ?spi interface slave ?hda bus the specific boot mode is sele cted based on the state of the irqd, irqc, irqb, and irqa pi ns at the time of reset de-assertion. the boot rom code has been designed to handle both encrypted and non-encrypted boot images from any of the above storage locations. boot modes are shown in table 6 on page 27 . the system requires external firmware to boot the internal dsp. internal rom within the dae-6 initiates the boot process to read the boot records and firmware, to load into the internal dae-6 memory. there are multiple boot modes provided on the dae-6 devices, as shown in table 6 . the mode is selected by a hardware pull-up or pull-down connection to each of the four boot mode (irq[d:a]) pins. (modes not listed are reserved.) boot sources include: ?i 2 c eeprom ? spi eeprom or spi flash ?i 2 c slave (to external microcontroller) ? spi slave (to external microcontroller) ? asynchronous uart (rs-232 fo r pc communication mode as well as d2-7xx83 device to device communication mode) ?hd audio bus ? combo mode with i 2 c eeprom or spi
d2-7xx83 27 fn7838.3 april 28, 2016 submit document feedback application firmware load the application firmware is loaded either by the boot code or by a multi-step process. direct boot code loading occurs when the selected boot mode successfully finds a boot image on the expected peripheral interface and the image is successfully loaded in memory. a multi-step boot is one in which the boot code loads a program that manages the system boot. control interfaces i 2 c 2-wire interface the d2-7xx83 family ic has two separate i 2 c 2-wire compatible ports. one is typically used fo r the external microcontroller interface, and the other for d2-7xx83 family ic communication to eeproms, or other compatible peripheral chips. both i 2 c interfaces are multi-master capable. registers are accessed through the i 2 c control interface. since the i 2 c bus has multiple slaves, the desired i 2 c target device must be addressed. the specific i 2 c channel control address is defined within the firmware that is loaded into the dae-6 at boot and initialization time. typical addresses used in various reference designs use the addr ess of 0xb2, but the actual address should be confirmed based on the firmware design being used in the application. serial peripheral interface (spi?) the serial peripheral interface (spi) is an alternate serial interface to the i 2 c interfaces. as a master, this interface supports port extenders, eeproms, flash, and various control interfaces for more complex chips. as a slave, this provides an alternate method for customers to communicate with the system. multi-controller ic communication the d2-7xx83 ic is capable of communicating and synchronizing data and control information acro ss multiple d2-7xx83 ics. this communication is to facilitate matr ix mixing of all input channels in a system and to allow precise phase alignment of the output audio. systems designs are capa ble of achieving outputs phase aligned to within 1/ 2 sample at 192khz. one d2-7xx83 ic acts as the timing master, so all other d2-7xx83 ics must then operate as timing slaves. the setting of the each of the d2-7xx83 ics is system-configuration specific and is detailed in the specific rdp documentation. audio synchronization multiple d2-7xx83 ics can be conn ected together and synchronized for controlling events to meet phase alignment requirements. control protocols provide for an external device communication with the d2-7xx83 firmware while the amplifier is running. the d2-7xx83 firmware has a periph eral device driver that establishes communication with the external controller device. the d2-7xx83 is always a slave. communication can occur through the hda, i 2 c, and spi ports. however control is provided through only the i 2 c, and hda ports, and control through the spi port is not supported. control register summary the control register interface provides a mechanism for an external controller to manipulate the amplifier signal flow, and provides access to the internal registers. each system design has its ow n firmware-dependent register application programming interf ace (api) and its own unique signal flow. the control register definitions, bit fields, and data format for each register are specified in that firmware api. table 6. boot modes mode irq[d:a] m/s xtali range interface speed description usage 0 0000 s n/a per master i 2 c port 1 slave boot at address 88 system 1 0001 m 24.576 mhz 400kb/s (see note 17 ) combo master - rom on i 2 c port 0 or spi system 2 0010 m 24.576mhz 1.53mhz rom on spi (ee or flash) (copy of mode 1 for pin compatibility) system 3 0011 s n/a per master spi slave boot system 7 0111 s 24.576mhz 384kb/s fast asynchronous sci boot multi-ic b 1011 s 24.576 mhz 9600 b/s asynchronous sci interface boot (rs232 compatible) system c 1100 m 24.576mhz 1.53mhz (see note 17 ) hda enabled, combo master - rom on spi (ee or flash) system d 1101 m 24.576mhz 400kb/s copy of mode c for pin compatibility system e 1110 m 24.576mhz per master hda boot system f 1111 m 24.576 mhz 400kb/s 2 wire rom on gpio port (scl= gpio1,sda = gpio0) system/ failsafe note: 17. for the ?per master? and ?n/a? entries above, there is a maximu m transfer rate that is a fraction of xtali speed. this maxim um transfer rate is peripheral port specific.
d2-7xx83 28 fn7838.3 april 28, 2016 submit document feedback reading and writing control registers registers and memory spaces are defined within the dae-6 firmware for specific internal operation and control. in typical reference designs, the highest-orde r byte of the register address (bits 23:16) determines the internal address space used for control read or write access, an d the remaining 16 bits (bits 15:0) describe the actual address within that space. refer to the descriptions of the actual refere nce design firmware being used in the application for specific definitions. all reads or writes to registers (shown in figures 10 and 11 ) begin with a start condition, followed by the device address byte, three register address bytes, three data bytes and a stop condition. register writes through the i 2 c interface are initiated by setting the read/write bit that is within the device address byte. the device write function as, shown in figure 10 , executes the following 9 steps as the i 2 c bus master: 1. i 2 c start command 2. transmit device i 2 c address with w 3. transmit mode byte 4. transmit upper memory address byte 5. transmit lower memory address byte 6. transmit data upper byte 7. transmit data middle byte 8. transmit data lower byte 9. i 2 c stop command all reads to registers require two steps. first, the master must send a dummy write, which consists of sending a start, followed by the device address with the wr ite bit set, and three register address bytes. next, the master must send a repeated start, following with the device address with the read/write bit set to read, and then read the next thre e data bytes. the master must acknowledge (ack) the first two read bytes and send a not acknowledge (nack) on the third byte received and a stop condition to complete the tran saction. the device's control interface acknowledges each byte by pulling sda low on the bit immediately following each write byte. the device read function, as shown in figure 11 , executes the following 11 steps as the i 2 c bus master: 1. i 2 c start command 2. transmit device i 2 c address with w 3. transmit mode byte 4. transmit upper memory address byte 5. transmit lower memory address byte 6. repeat start command 7. transmit device i 2 c address with r 8. receive data upper byte 9. receive data middle byte 10. receive data lower byte 11. i 2 c stop command or nack figure 10. i 2 c write sequence operation ack device-addr r/w ack register [15:8] ack register [7:0] start ack ack ack ack data [7:0] data [15:8] data [23:16] stop register [23:16] register [7:0] write sequence figure 11. i 2 c read sequence operation ack device-addr r/w ack register [15:8] ack register [7:0] start ack master ack nack data [7:0] data [15:8] data [23:16] stop register [23:16] ack repeat start repeat start device-addr r/w ack master ack step 1 step 2 read sequence
d2-7xx83 29 fn7838.3 april 28, 2016 submit document feedback audio processing functions each system design has its own firmware-dependent signal flow. this signal flow may be generic, or specifically designed for a particular amplifier application and consists of input elements connected to various signal proc essing blocks, routing the audio data to an output element. the input elements consist of chip peripherals used for audio input (i 2 s input, s/pdif digital receiver, and adc). the output elements include the chip i 2 s output, s/pdif digital transmitter, and pwm outputs. typical audio processing blocks include gain stages, mixers, tone controls, compressors, limiters, equalizers, routers, loudness contour, crossover filters, delays, as well as audio enhancement features provided within the specific application firmware. the input and output elements are configured by the firmware application and the scope of i/o selection is generally specific to the hardware of the pa rticular application. the signal processing blocks co ntain one or more parameters that define the signal transfer characteristic of the block and a mechanism for choosing the source and destination data locations. the signal flow is cr eated by connecting together the signal processing blocks in th e proper order to achieve the overall system audio processing function. firmware functions d2-7xx83 ic contains a dsp supporting powerful audio processing algorithms. some of the standard audio algorithms that are typically supported in all firmware loads. other algorithms are specific system design and firmware load dependent. additional features support multiple system capabilities such as: ? automatic power-on amplifier calibration ? parameter control and status reporting ? integrated power supply control and clock synchronization ? automatic power supply high-voltage rail anti-pump control ? automatic negative rail generation and bring-up control (for select half-bridge designs where a rail is not already supplied) ? automatic cycle-by-cycle temperature sensing and system response ? automatic cycle-by-cycle current sensing and system response ? input audio signal sensing and pop-free power-on/off via d2audio?s patented ?green mode ? algorithm with adjustable threshold ? dynamic adjustment of efficiency vs. distortion vs. output power level via d2audio?s patented ?dynatiming? algorithm ? am radio interference avoidance mode allows for dynamic switching of pwm engines when system microcontroller is in am radio model input source selection a source selection re gister specifies the action of a signal multiplexer, which will implement a simple switching function. the selected input will be routed to the block output unaltered. all non-selected inputs will be ignored. selections typically include i 2 s inputs, s/pdif digital inputs, hd audio inputs, and adc inputs. master volume a master volume function alters the level on all channels simultaneously by applying the same gain/attenuation function to each. a single parameter controls all channels. channel attenuation a channel attenuation function alters the level of a single channel. a single parameter is provided for each channel. equalization an equalization proce ssing block consists of a single input and output, and is characterized by how many frequency bands are supported. typical equalizers have 3-bands or 5-bands, although multiple combinations are direct ly supported. each frequency band has 3 parameters - the center frequency, the filter q, and the filter gain. tone control tone control provide simple bass and treble processing to the audio signal. each tone processing block includes two first-order (6db/octave) shelving filters, one each for bass and treble. filters include programmable corner frequency and gain settings. excursion control excursion processing provides dynamic control of the subwoofer response. three audio processi ng control adjustments are provided for frequency settings, and three adjustments are provided for q parameter settings. mixer mixer configuration blocks have multiple input channels and as many output channels as required by the system implementation. the mixer has an input gain parameter for each input to every mixing node. (e.g. an 8-input mixer with 12 outputs incorporates a total of 96 independent gain adjustment parameters.) the minimum gain parameter value is infinite attenuation, or mute. mixers an input mixer provides a two-input, two-output mixing and routing path. all inputs can be mixed at adjustable gain into any combination of outputs. programm able settings are continuously adjustable from unity (0 db) gain, through full cut-off. compressor/limiter the compressor/limiter processor is used to gracefully limit the dynamic range of the audio signal. this is useful to prevent the amplifier from clipping or to limit the amplifier output power. each compressor/limiter has conf igurable compression ratio, threshold, attack and release time, as well as makeup gain.
d2-7xx83 30 fn7838.3 april 28, 2016 submit document feedback upward compressor upward compressors provide audio compression and limiting functions but also provide an incr ease of signal level to inputs below the threshold setting. upward compressors have configurable expansion ratio, threshold, attack and release time, as well as makeup gain. co ntrols are supported for global settings, gate adjustment, and for low level expansion. upward compressors support two inputs. one input receives the audio that is processed by the compressor and passed to its output. a separate side chain input is used as the reference input for the processing algorithms. delay a delay block simply adds delay to the audio signal. a single delay parameter is used. crossover low-pass and high-pass filter blocks add frequency filtering to the audio paths, providing appr opriate signal processing for speaker crossover functionality, including bi-amplified solutions, and subwoofer low-pass filtering. high/low-pass filters high-pass and low-pass filter blocks are provided for each of the 5 output channels downstream of the router and stereo mixer. these provide a flexible crossover function for all the output channels, including provision for defining the subwoofer channel?s frequency response. filters are implemented as cascaded elements, with elements allocated for high-pass as well as for low-pass functionality, with complete flexibility of assignment. pre-defined filter types including butterworth, be ssel, and linkwitz-riley implementations are also provided. routers routers provide individual audio path selection to any one of available input channels. the router performs path assignment only. it does not have a provision for gain or signal level adjustment. loudness contour loudness contour provides adjustment to allow for dynamically and automatically enhancing th e frequency response of the audio program material relative to the master volume level setting. the loudness contour models the frequency response correction as defined by the fletcher/munson audio response curve. it provides for amplitude or volume changes to those signals to which the ear does not respond equally at very low listening levels. audio processing enhancements and decoding depending on the device part number and design-specific firmware definitions, the dae-6 device supports a variety of processing, decoding, virtualization, and pre/post processing feature sets, as well as option s for dsp clock speed and memory capacity. features and proce ssing support are shown in ? dae-6 device feature set offering ? on page 3 . soundsuite? processing the d2audio soundsuite? audio processing provides a full set of enhancements to audio that greatly add to the quality and listening experience of sound in wide scopes of consumer devices. the d2audio soundsuite? algorithms use psycho-acoustic processing that create a rich-sounding environment from small speake rs, and synthesizes the sound and quality equivalent to more co mplex systems. it is especially suited to consumer products that include televisions, docking stations, and mini hi-fi stereo products. the dae-6 includes enhanced soundsuite processing that includes: ? d2audio? widesound? ? d2audio? deepbass? ? d2audio? audioalign? ?d2audio? clearvoice? the d2audio?soundsuite? algorithms are completely included within the d2-71083 and d2-74083 dae-6 devices. mark levinson mightycat? processing the mark levinson mightycat? se ries of processors provide an exclusive set of mastering tools and tuning capabilities, and have been developed and refined by mark levinson over the course of his many years of reco rding experience. the tools and capabilities allow for an extended studio quality tuning that is only available in the mightycat? series of dae-6 processors. the mightycat? algorithms are included within the d2mc-72083 and d2mc-76083 devices. refer also to the ? dae-6 device feature set offering ? on page 3 .
d2-7xx83 31 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7838.3 april 28, 2016 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . disclaimer for dolby technology license required notice: intersil may distribute dolby? technology separately from its d2 audio? integrated circuits. dolby? technology would be embedded in firmware to be loaded onto and executed by dolby? enabled d2au diotm integrated circuits. supply of this implementation of dolby technology does not convey a license nor im ply a right under any patent or any other industrial or intellectual property right of dolby laboratories to use this implementation in any finished end-user or ready-to-use final product. it is hereby notified that a li cense for such use is required from dolby laboratories. in some cases the dolby? technology may include at least one dolby? pro logic? decoder. the party receiving this implementation must be licens ed for at least one of the three dolby laboratories licensing corporation (?dolby?) technologies contained in this implementation. if the party receiving this implementation is not a licens ee for all three of the dolby technologies contained in this implementation then the party may only use the unlicensed technology(ies) con tained on the implementation for internal testing and evaluation purposes. disclaimer for dts (srs) techno logy license required notice: notice of license requirement: supply of this implementation of dts technology to dts product licensees directly or through a distributor does not incur a royalty payment or convey a license, exhaust dts? rights in the implementation, or imply a right u nder any patent or any other industrial or intellectual property right of dts to use, offer for sale, sell, or import such implementatio n in any finished end-user or ready-to-use final product. a license from and royalty payment to dts is required prior to and for such us e. revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go to web to make sure you have the latest revision. date revision change april 28, 2016 fn7838.3 updated the ordering information table on page 2. updated table 1 on page 3 algorithm support column for d2-71583-lr, D2-74583-LR and d2-71683-lr. replaced the products section wi th the about intersil section. added dolby and dts disclaimers. september 20, 2011 fn7838.2 revise/add available de vice part numbers and related descriptions. june 23, 2011 fn7838.1 initial release.
d2-7xx83 32 fn7838.3 april 28, 2016 submit document feedback low plastic quad flatpack packages (lqfp) d e d1 e1 e 128x b l (l1) a1 a2 a r2 r1 s 02 0 3 b1 c1 c b 1 32 33 64 65 96 97 128 seating plane y 0.080 y detail f detail f 124x 0.25 gauge plating 0.05 0.07 y t-u z u t 0.2 h t-u z 4x 0.2 y t-u z 4x h plane 01 0 pin 1 m q128.14x14 128 lead low plastic quad flatpack package .4 mm pitch symbol millimeters notes min nom max a - 1.60 - a1 0.05 0.15 - a2 1.35 1.40 1.45 - b 0.13 0.16 0.23 4 b1 0.13 - 0.19 - c 0.09 - 0.20 - c1 0.09 - 0.16 - d 16 bsc - d1 14 bsc 3 e 16 bsc - e1 14 bsc 3 l 0.45 0.60 0.75 - l1 1.00 ref - r1 0.08 - - - r2 0.08 - 0.20 - s0.20--- 003.57- 01 0 - - - 02 11 12 13 - 03 11 12 13 - n 128 - e0.40 bsc- rev. 1 7/11 notes: 1. dimensions are in millimet ers. dimensions in ( ) for reference only. 2. dimensions and tolerances per amsey14.5m-1994. 3. dimensions d1 and e1 are excluding mold protrusion. allowable protrusion is 0.25 per side. dimensions d1 and e1 are exclusive of mold mismatch and deter- mined by datum plane h. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar cannot be located at the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07 mm.

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